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a
FEATURES -2 V to +7 V Input Voltage Range Low V IN Bias Current (<100 nA) Up to 5 V/ns Input Signal Tracking Low Dispersion of 100 ps 28-Lead PLCC Package APPLICATIONS Automatic Test Equipment Semiconductor Test Systems Board Test Systems
High Speed Window Comparator AD53042
FUNCTIONAL BLOCK DIAGRAM
GND LEA LEA NC +VS NC GND GND QA LATCH/OUTPUT A QA DGND QB LATCH/OUTPUT B QB GND GND VA NC VIN NC VB GND
AD53042
LEB LEB NC NC -VS GND GND NOTE: NOT THE ACTUAL PHYSICAL LAYOUT OF DEVICE. NC = NO CONNECTION INSIDE PACKAGE.
PRODUCT DESCRIPTION
The AD53042 is an ultrahigh speed window comparator with latch. It uses a high speed monolithic process to provide high dc accuracy without sacrificing input voltage range. On-chip connection of the common input eliminates the contributions of a second bonding pad and package pin to the input capacitance, resulting in a maximum input capacitance of 2 pF. The AD53042 employs a high precision differential input stage with a common mode range of 9 V. Its complementary digital outputs are fully ECL-compatible. The output stage is capable of driving a 50 line terminated to -2 V. The device also provides a latch function, allowing operation in track-hold mode and can also be used to generate hysteresis.
3.0V 2.8V MIN. POSITIVE INPUT PULSE
0V
3.0V
MIN. NEGATIVE INPUT PULSE 0.2V
0V
Figure 1. Typical Application Circuit
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
apply = 40 C to 100 C AD53042-SPECIFICATIONS (All specifications-7.7 V with T otherwise noted.)and +V = +7.75 V to +11.5 V; -V = -3.95 V to unless
C S S
Parameter POWER SUPPLIES Positive Supply Currents Negative Supply Current Power Dissipation DC INPUT CHARACTERISTICS Offset Voltage (VOS) VIN Bias Current VA, VB Bias Current Capacitance VIN, V A, VB Voltage Range (VCM ) Differential Voltage (VDIFF) Nonlinearity VA/VB Interaction BIAS CURRENT Change vs. Comparator State Nonlinearity Tempco LATCH ENABLE INPUTS Common-Mode Range Differential Voltage Logic "1" Current (LIH) Logic "0" Current (LIL) DIGITAL OUTPUTS Logic "1" Voltage (VOH) Logic "0" Voltage (VOL) SWITCHING PERFORMANCE Propagation Delay Input to Output Latch Enable to Output Part-to-Part Skew Change vs. Temperature DISPERSION 5 V p-p Input (All Edges) 5 V p-p Input (All Edges) V Slew = 1 V/ns (All Edges) V Slew = 1 V/ns (All Edges) Minimum Pulsewidth Edge Interaction Duty Ratio Comparator Interaction
Min
Typ
Max 65
Units mA mA W mV A A pF V V mV mV/V A A A/C V V A A V V
Test Conditions No Load No Load No Load, +VS = +10 V, -VS = -5.2 V CMV = 0 V VIN = 0 V VIN = 0 V
-85 1.19 -10 -0.5 -20 -VS + 2.7 -5 10 0.5 20 2 +VS - 2.5 9 5 0.1 1 2
<0.1
See Note 1
-1 -2
0.1
-2 0.4 -10 -0.98
1 3 200
-1.5
Q or Q, 50 to -2 V Q or Q, 50 to -2 V
2 1.2 1 100 175 50 50 <1 <200 <100 <100 1
ns ns ns ps/C ps ps ps ps ns ps ps ps
VIN = 2 V p-p, tPDR, tPDF, Figure 1, Note 2
10%, 90% 0.5 V/ns, 3 V/ns 10%, 90% 5 V/ns 10%, 90% 3 V, 5 V 20%, 80% 1 V See Note 3 See Note 4 See Note 5
NOTES 1 Defined as change in V OS from -VS + 2.95 V to +VS - 2.75 V (throughout the range) after V A and VB are corrected for gain and offset using 0 V and 5 V. 2 Propagation delay is measured from the input threshold crossing at the 50% point of a 0 V to 5 V input to the output Q and Q crossing. 3 The minimum input pulsewidth that will maintain a 600 mV ECL swing on the output. The input is a 0 V to 3 V signal with a 3 V/ns rise and fall times. The input pulsewidth is measured between the 2.8 V point of a positive input pulse and the 0.2 V of a negative input pulse. See Figure 2. 4 Maximum Change in propagation delay as the input pulse is reduced from 50 ns to a 2 ns pulsewidth. 0 V to 3 V swing with 3 V/ns rise/fall time and 25% duty cycle. 5 Maximum Change in propagation delay as the input pulse is reduced from 99% to a 1% duty cycle. 0 V to 3 V swing with 3 V/ns rise/fall time and 50 ns to 4.95 s pulsewidth, period = 5 s. Specifications subject to change without notice.
-2-
REV. A
AD53042
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
Shipment Method, Quantity Per Shipping Container Tube, 36 Pieces
Power Supply Voltage +VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V -VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8 V +VS to -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V Inputs VIN, VA, VB . . . . . . . . . . . . . . . +VS - 13.5 V, -VS + 13.7 V LEA, LEA, LEB, LEB . . . . . . . . . +VS - 14 V, -VS +10 V Currents +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 mA -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -75 mA QA, QA, QB, QB . . . . . . . . . . . . . . . . . . -40 mA to +2 mA Environmental Operating Temperature (Ambient) . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . -65C to +125C Lead Temperature (Soldering, 20 sec) . . . . . . . . . . . +300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Absolute maximum limits apply individually, not in combination. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The device must suffer no reliability degradation if any supply pin is either shorted to ground or left floating for an indefinite periods of time during normal operation.
Model AD53042KRP
Package Description 28-Lead PLCC
Package Option P-28A
PIN CONFIGURATION
VPOS GND LEA GND 25 GND 24 QA 23 QA 22 DGND 21 QB 20 QB 19 GND 12 13 14 15 16 17 18 LEB LEB NC VNEG GND NC = NO CONNECT GND NC LEA NC NC
4 GND 5 VINA 6 NC 7 VINAB 8 NC 9 VINB 10 GND 11
3
2
1
28 27 26
PIN 1 IDENTIFIER
AD53042
TOP VIEW (Not to Scale)
LEA, LEB LEA, LEB VIN VA VB
VA VB VIN QA
tPDR
tPDF
~1.2ns
QA
QA QB QB
tPDR
tPDF
QA QB QB
Figure 2. Timing Diagram I
Figure 3. Timing Diagram II
If either of the latch enables, LEA or LEB are low, the output follows the input. If LEA or LEB are high, the comparator outputs will be latched and they won't change.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD53042 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
AD53042
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
4 5 PIN 1 IDENTIFIER
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07)
26 25
0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33)
TOP VIEW
(PINS DOWN) 11 12 19 18
0.050 (1.27) BSC
0.032 (0.81) 0.026 (0.66)
0.430 (10.92) 0.390 (9.91)
0.020 (0.50) MAX (3) PLACES
0.456 (11.58) SQ 0.450 (11.43) 0.495 (12.57) SQ 0.485 (12.32)
0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
-4-
REV. A
PRINTED IN U.S.A.
C3120a-0-5/99
28-Lead Plastic Leaded Chip Carrier (P-28A)

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